Refactor: Adjust bootrom reset vector address

Support outer-buffers for spad

Support TLbuffer for scratchpads

Support sub-banking spads

Add config/class to instantiate our own EICG_wrapper

The Rocket-chip one sometimes doesn't include the resource file, ours always does

Split debug_tick from rest of code

Remove implicit Parameters from some harness blocks

Support deduping spad banks

Remove HarnessAXIRAM stuff

Now that multi-top sims in CY are supported, this is redundant with the
Chip+Bringup multi-chip configs, which is the preferred way to go about
this moving forwards

Add API to configure TLSerial bundleParams | TLSerial debug IO

* This makes backwards-compatibility with older chips easier

Merge commit 'c80ec1cd' of https://github.com/ucb-bar/testchipip into HEAD

Print fixes and remove extra includes

Fix banked scratchpads

Add cospike implementation