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tsi_chipyard

6af91953 · WIP, start adding TSI traits · Apr 29, 2020

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update-gitignore

ebad2d3d · Ignore vim swap files · May 05, 2020

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spiflash_all_c

2b391c6b · WIP · May 06, 2020

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RC-1.3-bump

5b3f2c96 · allow different buffer parameters to be set again · May 13, 2020

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rc-retile

29eb87c9 · Bump Rocketchip to June 2020 · Jun 19, 2020

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fast-program-load

cf2e461b · serial writes directly to DRAM for fast program loading · Jul 11, 2020

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rc-july2020

1e7373f6 · Better string concatenation · Aug 27, 2020

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sbus-ring-membench

05588902 · fix DRAMSim2 write address handling · Sep 03, 2020

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tsi-source-setter-beagle

a9adf2b3 · Adding monitor to keep D signals · Sep 11, 2020

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serial-clock-fix

a86c827c · Fix ClockedIO cloneType · Sep 12, 2020

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serial-tl

bdca33ec · Remove TLBuffer unnecessary argument · Sep 17, 2020

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bootrom-dump

28b44293 · Makefile should generate bootrom objdump by default · Sep 24, 2020

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pbus-tl-mem

bd0ff2d0 · Add config to hang the serial TL mem off the PBus for the no-L2 case. · Sep 25, 2020

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diplomatic-clocks-dram

8f489545 · Add a form of ClockedIO with reset · Sep 29, 2020

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tile-reset-ctrl

b3aa1bea · Remove bootrom dumps · Oct 01, 2020

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unify-fesvr

56bfaa3f · Rename testchip_fesvr to testchip_tsi · Oct 09, 2020

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block-dev-multiclock

b178da62 · [blkdev] Break assumption that client domain == manager domain · Nov 07, 2020

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chisel34-bump

6fbb1b77 · Cleanup build.sbt | Bump versions · Nov 30, 2020

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no_supervisor_bootrom

00103634 · Bootrom support for systems with no S-mode (no MIDELEG) · Dec 22, 2020

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add-ci

3a949dfb · Reduce heap size · Dec 29, 2020

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