Verilator ignores these delays (after warning the user), so they can
result in race conditions.

Co-authored-by: Ernie Edgar <ernie.edgar@sifive.com>

User fields on C channel

Since the CacheCork does not hard-code this, the cache should.

This was a total hack. Let's do things properly.

We are still experimenting with user bits in the TL-C setting.

However, it does appear necessary to control these bits at the very least
for Releases and ProbeAcks which get transformed into Puts.

- convert to chisel3
- upstream factory helper from sifive-blocks
- improve detail of scaladoc comments

Add maxTransactionsInFlight to IDMapEntry and OMIdMapEntry

Debug: Make reset synchronizer instanatiation optional

L1TLB: fix support for configurable Sets/Ways

consistent parameter names for API consistency: rename TLBConfig nEntries -> nWays; OMCaches keep nTLBEntries for backwards compatibility

L1 TLB: Add support for configurable L1 TLB (sets/ways)

PTW: wait for L2TLB refill before searching

bug fix for ClockDivider

Nodes Documentation (see #2308 #2560)