* adding cover points for access modes with lock bit set high

* remove the default condition for access and permission cover points

* ntlbentries removed from cache trait

diplomacy: don't auto-punch ephemeral node wires

* haslogicaltreenode

This reverts commit ff652979.

This reverts commit 0951c283.

They don't go anywhere, so don't plumb them uselessly to the top!

Add scalastyle-sbt-plugin.

Fix weird merge issues with logical-tree3

This reverts commit 0db73aaf.

This reverts commit aa459e01.

This reverts commit 80710752.

* A replacement for the previous object model structure. the new structure is distributed and does not rely on a traversal of the design except in the core for now (this may be replaced as well). Relationships between parents and children are stored and later traversed. The same getOMComponents functions are called but not in device rather they have been moved to a LogicalTreeNode associated with the design component.

Ephemeral nodes

In principle, clients should not reference chisel3.core directly. In the case of DontCare, we want to force references to the definition in the chisel3 package to avoid having DontCare defined as a user node.

Avoid explicitly creating entire DM flags array

This also constant-propagates through the async crossing.

This is now legal, since it is a WARL register.

This commit reduces the amount of Verilog that gets generated by about
200 KB.  It should have no semantic impact.  (The regmapper uses explicit
base addresses for each field, so changing the size of the array doesn't
affect the generated memory map.)

Quick fix for https://github.com/freechipsproject/chisel3/pull/1040 which adds scalastyle settings.

Support non-power-of-2 data scratchpads

Memory system features