* adding global storage of components not in the logical tree

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>

* Don't accept DMI response when DMI Busy error bit is set.
* DebugTransport code cleanup

Support CFLUSH.D.L1 rs1 address argument

When rs1 = x0, it flushes the whole cache.

When rs1 != x0, it flushes the line containing the address in rs1.

generator: support the no rocket tiles case

Get L2 TLB parity check off the critical path

Close #1817

* PSDTestMode: Add a Config knob for the PSD Bundle Broadcast

* PSDTestModeBroadcastKey: update field type

Adding cover points for pmp permission, and access

Removing the CSR.R as a measure of accessing the csr

* Bump verilator to 4.008

* update verilator opt, which more user friendly

* Update thread number for unittest design for travis test

Minor QoR improvements

When simulating with iverilog, we get an error message for the
assignment to _RAND in the module's initial block:
"Variable declaration in unnamed block requires SystemVerilog."

Provide a name (":B0") for the initial block, which should be a
syntac no-op for already supported simulators, and allow also
running simulations under iverilog.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>

derp

It is instead merged into the way mux.