Commits · tile-reset-crossing-type · github.com / ucb-bar / rocket-chip · GitLab

Nov 14, 2020
- update imports based on scalafix after rebasing · ce076063
  Henry Cook authored Oct 28, 2020
  
  ce076063
- tile: use BundleBridgeBlockDuringReset for tile trace interfaces · fd9d3063
  Henry Cook authored Sep 28, 2020
  
  fd9d3063
- util: BlockableTraceCoreInterface · d7bc741e
  Henry Cook authored Sep 28, 2020
  
  d7bc741e
- util: type class implicit Blockable · 3bccd853
  Henry Cook authored Sep 25, 2020
  
  3bccd853
- differentiate ClockCrossingHelpers from ResetCrossingHelpers · a57f0f6a
  Henry Cook authored Sep 18, 2020
  
  a57f0f6a
- diplomacy & prci: adjust crossingtype locations and type hierarchy · f9bc0f7a
  Henry Cook authored Sep 18, 2020
  
  f9bc0f7a
- tile: preserve bind query on slaveNode · 07e8aef5
  Henry Cook authored Sep 16, 2020
  
  07e8aef5
- util: fix blockduringreset counter to saturate · 61346766
  Henry Cook authored Sep 16, 2020
  
  61346766
- Revert "Ensure trace.valid is 0 during async reset" · 6befa6b2
  Henry Cook authored Sep 16, 2020
```
This reverts commit e3d506da.
```
  6befa6b2
- prci: add ResetCrossingType and use with CrossingHelpers to control BlockDuringReset presence · 9321d83c
  Henry Cook authored Sep 16, 2020
  
  9321d83c
- diplomacy: CreditedCrossing implies same clock · 9729d361
  Henry Cook authored Sep 16, 2020
  
  9729d361
- block during reset supports blocking for a stretched amount of cycles · 9aae2881
  Henry Cook authored Sep 14, 2020
  
  9aae2881
- interrupts: IntTempNode · dfd51d2e
  Henry Cook authored Sep 16, 2020
  
  dfd51d2e
- rational crossing: dont BlockDuringReset deq · b2fab7eb
  Henry Cook authored Sep 16, 2020
  
  b2fab7eb
- prci: get more aggresive with shouldBeInlined for various adapters and wrappers · f9881faf
  Henry Cook authored Sep 14, 2020
  
  f9881faf
- Expose control over take field for all ClockSinkParameters · b2672674
  Jerry Zhao authored Aug 24, 2020
  
  b2672674
- prci: alternate clock domain constructors · 45fcbc0e
  Henry Cook authored Sep 11, 2020
  
  45fcbc0e
- tile: provide reset domain container · ff7b9d67
  Henry Cook authored Sep 11, 2020
```
intended to hold all BlockDuringReset components that need to be asynchronously reset
```
  ff7b9d67
- update BlockDuringReset and add TL and Interrupt versions · 7e99ed0a
  Henry Cook authored Sep 11, 2020
  
  7e99ed0a
- Revert "Use unmodified, possibly async reset for notification ports" · 694ee845
  Henry Cook authored Sep 08, 2020
```
This reverts commit 16329253.
```
  694ee845
- Revert "Revise trace.valid gating method to relieve timing on reset" · 21a89860
  Henry Cook authored Sep 08, 2020
```
This reverts commit ede4d59a.
```
  21a89860
- Revert "Move beu interrupt crossing source register into Tile" · cfddea34
  Henry Cook authored Sep 08, 2020
```
This reverts commit c8f7e470.
```
  cfddea34
- Move beu interrupt crossing source register into Tile · f05453e7
  Ernie Edgar authored Aug 30, 2020
  
  f05453e7
- [prci] Provide ibus clock from sbus in BaseSubsystem · 70406180
  David Biancolin authored Nov 13, 2020
  
  70406180
- Have InterruptBusWrapper extend ClockSinkDomain · 6d1d25d2
  David Biancolin authored Nov 12, 2020
  
  6d1d25d2
- [prci] Provide a require message for ClockGroupAggregator when in.size =/= 1 · 58a41993
  David Biancolin authored Nov 08, 2020
  
  58a41993
- Eschew use of subsystem implicit clock in CLINT · c9a9bd75
  David Biancolin authored Nov 08, 2020
  
  c9a9bd75
- Eschew use of subsystem implicit clock in HasPeripheryDebug · f034c096
  David Biancolin authored Nov 08, 2020
  
  f034c096
- Eschew use of subsystem implicit clock in PLIC + IntBus Wrapper · ee32850c
  David Biancolin authored Nov 08, 2020
  
  ee32850c
- Eschew use of subsystem implicit clock in BootROM · 64171426
  David Biancolin authored Nov 08, 2020
  
  64171426
- Eschew use of subsystem implicit clock for RTC mixin · 495733b4
  David Biancolin authored Nov 08, 2020
  
  495733b4
- Merge pull request #2718 from chipsalliance/plic-reg-descs · b5d797a4
  Megan Wachs authored Nov 13, 2020
```
PLIC Priority RegFieldDesc fix off-by-one
```
  b5d797a4
- Merge pull request #2729 from chipsalliance/elaboration-artefacts-renames · 71218bea
  Henry Cook authored Nov 13, 2020
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allow renames to multiple targets for MemoryPathToken
```
  71218bea
- PLIC: add missing comma · e1967aa8
  Megan Wachs authored Nov 10, 2020
  
  e1967aa8
- Update src/main/scala/devices/tilelink/Plic.scala · 942708d6
  Megan Wachs authored Nov 09, 2020
  
  942708d6
- PLIC: explicitly name priority registers to avoid off-by-one confusion · 017c962b
  Megan Wachs authored Nov 09, 2020
  
  017c962b
- Plic: use named constant instead of hardcoded value · d1c0c318
  Megan Wachs authored Nov 03, 2020
  
  d1c0c318
Nov 13, 2020
- NMI implementation (#2711) · 12da135d
  Ernie Edgar authored Nov 13, 2020
  
  12da135d
- Rocket updates for zfh (#2723) · 63b76488
  Kira Tsao authored Nov 13, 2020
  
  63b76488
- Merge pull request #2730 from chipsalliance/fix-pwr-vipt · 614f2fd8
  Andrew Waterman authored Nov 12, 2020
```
Fix regression introduced by 40749694 for M_PWR commands
```
  614f2fd8