util: fix errors during FIRRTL pass

Assorted fixes for scala 2.13/chisel 3.5.5

Explicitly use python3 for mem gen scripts

Co-authored-by: phthinh <hung3@e.ntu.edu.sg>
Co-authored-by: Yangyu Chen <cyy@cyyself.name>
Co-authored-by: Jerry Zhao <jerryz123@berkeley.edu>

Bump verilator and rocket-tools

Related to https://github.com/chipsalliance/rocket-chip/issues/3228

* Bump verilator to 4.226; However, as spike recently needs
c++17, and verilator selects the c++ version based on Linux
distribution, we have to manually set it by CFG_CXXFLAGS_STD_NEWEST

* Bump rocket-tools to latest; This introduce the c++17 spike.

Ref to https://github.com/chipsalliance/rocket-chip/pull/3193

Populate tval with pc when ebreak

Generate correct lazyscope name

This reverts commit 69d260fa.

s1_req is not TLBReq and should be manually connected

Fixes https://github.com/chipsalliance/rocket-chip/issues/3165

+ replace .getPorts with DataMirror.modulePorts;

mill: enable zicntr test for TinyConfig

See https://github.com/chipsalliance/rocket-chip/pull/3202