RoCC PTW refactoring

More travis fixing

I hope this will result in Travis building our stuff a lot faster, since this
currently takes about half the time.

travis-ci.org improvements

This uses the compiled tests in RISCV, which match the rest of the toolchain.

We want to add support for caching riscv-tools builds on Travis and the easiest
way to do so looks like to jus go ahead and use

The FPGA doesn't have an HTIF clock divider

We used to just be writing the SCR anyway, but now that the SCR maps are
automatically defined VCS will detect the missing SCR and bail out when
compiling test harness code.  This patch just doesn't write the HTIF SCR when
there isn't one.

We're building a chip with 8 memory channels.  Since this will require a
complicated test setup we want to also be able to bring up the chip with fewer
memory channels.  This commit adds a SCR that controls the number of active
memory channels on a chip.  Toggling this SCR will scramble memory and drop
Nasti messages, so it's only possible to change while the chip is booting.

By default this just adds a 1-bit SCR, which essentially no extra logic.

When multiple memory channel configurations are enabled at elaboration time, a
NastiMemoryInterconnect is generated for each channel configuration.  The
number of outstanding misses is increased to coorespond to the maximum number
of banks per memory channel (added as a parameter), which I believe is
necessary to avoid deadlock in the memory system.

A configuration is added that supports 8 memory channels but has only 1 enabled
by default.

Without this I don't get rebuilds when toching a file in CDE.

This uses the new SCRFile changes to generate a header file containing a list
of all the SCRs in a core to remove the magic constant "63" (the HTIF clock
divider control register) and replace it with a generated number (which is
still 63).

This reverts commit 4dad5b8b.

The commit breaks the build.

This reverts commit 4d0f941d.

The commit breaks the build.