A "size=(1<<31)" returns a negative integer size (and errors out in FIRRTL),
while size=(1<<32) wraps around back to 1 (instead of getting a 4B entry RAM).

Since comically large SRAMs aren't desirable anyways (and difficult to
simulate), let us place assertion guards on the caller side of the RAM creation.

riscv-tests: bump for fix in multi-hart test

* PSDTestMode: in Debug Module, bypass dmactive reset during PSDTestMode

Debug: fix polarity of dmactive as reset

* ResetCatchAndSync: alwayas apply DFT bypass to flops inputs

Fixup cases where Acquire.NtoB is incorrectly promoted to Grant.toT

Previously, using the BusBypass, the PhysicalFilter tried to cut all
traffic (including B+C). This was wrong.

Now, we carefully wait until A=>D is idle, then swallow denied traffic.
The injected traffic thus respects order and we swallow any GrantAcks.

This device will soon not be derived from the BusBypass.

If a WidthWidget ever ends up needing to bypass, it would have
coupled a.ready => a.fire() => bypass => d.bits.

That's both illegal and unnecesary.

Handle TL errors better in D$

Closes #1429.

debug: assert on unexpected exceptions

Travis: fix indentation

Harts should only be writing to the EXCEPTION location if doing work under the direction of the debugger.

Debug: fix the location of the exception assertion

Debug: fix the assertion comparison

Debug: move assertion to right spot

* Added emulator debugging with GDB documentation

This documents the process of debugging RISC-V programs against the GNU debugger with OpenOCD.
https://github.com/freechipsproject/rocket-chip/issues/1339

* Review 1 by Megan.

review 1

* The executable arg is a dummy arg when using RBB emulator

* testing programs on emulator + reducing size ideas

+ Pointed out that {more size --> more execution time} and a solution.
+ Separated simple programs execution and testing (step 2) of program debugging (step 3): To illustrate the fact that custom programs can be run on the emulator too not only the benchmarks.

* typo minor change

* Modifications

Added an example command of VCD output + log file generation
Rearranged VCD size idea into the part where I talk about executing/testing
Cleaned redundancies

OpenOCD Sim Speedup & RISC-V Tests Bump

* modifying the regmapper annotations

* fixed an indentation issue

Don't raise the single-step interrupt when in debug mode

This only affects cores that are capable of taking two interrupts on
back-to-back cycles, i.e., not Rocket.

tilelink: split error into denied and corrupt

A bad address in TileLink should use 'denied', not 'corrupt'.
Unfortunately, TLFragmenters cannot reassemble denied AccessAckDatas.

Since these are almost always used in conjunction, SRAMs can no
longer generate addressing errors. However, they can now both
track the 'corrupt' status of memory.

RegField: Allow description to be passed in to AsyncRWSlaveRegField