- Feb 06, 2019
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Derek Pappas authored
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- Feb 01, 2019
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Andrew Waterman authored
derp
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Andrew Waterman authored
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Andrew Waterman authored
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Andrew Waterman authored
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Andrew Waterman authored
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Andrew Waterman authored
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Andrew Waterman authored
It is instead merged into the way mux.
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- Jan 31, 2019
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Jack Koenig authored
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Derek Pappas authored
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- Jan 30, 2019
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Andrew Waterman authored
Encapsulate PMP reset
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Derek Pappas authored
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Srivatsa Yogendra authored
Bumping riscv-tools
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- Jan 29, 2019
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Srivatsa Yogendra authored
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Andrew Waterman authored
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- Jan 26, 2019
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Andrew Waterman authored
This facilitates moving emulation code out of the M-mode trusted codebase.
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- Jan 25, 2019
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Henry Cook authored
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- Jan 23, 2019
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Gleb Gagarin authored
* Moved CoreMonitorBundle class to util package
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- Jan 22, 2019
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Derek Pappas authored
* adding cjtag
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Albert Chen authored
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- Jan 19, 2019
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Derek Pappas authored
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Aliaksei Chapyzhenka authored
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- Jan 18, 2019
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Gleb Gagarin authored
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Andrew Waterman authored
Respect SEIP during WFI clock gate
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Sandeep Rajendran authored
rename ahb_fuzzing plusarg
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- Jan 17, 2019
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Andrew Waterman authored
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Andrew Waterman authored
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Sandeep Rajendran authored
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Sandeep Rajendran authored
Add plusarg option to disable fuzzing
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Derek Pappas authored
* adding registers to the OM
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Sandeep Rajendran authored
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- Jan 16, 2019
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Wesley W. Terpstra authored
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Andrew Waterman authored
Minor QoR improvements
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Andrew Waterman authored
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Derek Pappas authored
* changing where getOMComponents is called in the flow
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- Jan 12, 2019
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Andrew Waterman authored
s2_xcpt doesn't need to drive so many things.
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Ryan Macdonald authored
Trace: suggestName trace node
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Ryan Macdonald authored
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- Jan 09, 2019
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Jack Koenig authored
Bump chisel3
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- Jan 08, 2019
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Jack Koenig authored
Summary of changes: * Basic BundleLiteral support * Add lit*Option methods for extracting literals * Improved numbering of _T_* * Undeprecate log2Up and log2Down * BoringUtils for synthesizable cross module references * Seq[Data] illegal in Bundle, override with ignoreSeq * MixedVec * Module Inlining and Flattening Support * Verilog memory loading * Access module ports via DataMirror.modulePorts * Support for .B on [Big]Ints * Stack Trace Trimming * toBool[s] -> asBool[s] * Improved UInt.-% emission
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