SContext is remaps to HContext when in VSMode

* Fix the mapping when we access scontext or hcontext to ensure we don't switch targets.
* Add comment to indicate why we are mapping the S to VS and VS to S.

Remove Scalar Crypto and BitManip (copy #3532)

(cherry picked from commit 218ae0aa)

(cherry picked from commit 5bef59a8)

# Conflicts:
#	src/main/scala/tile/Core.scala

(cherry picked from commit 74dd9b19)

(cherry picked from commit df66c19e)

Add DelayQueue (backport #3520)

(cherry picked from commit 4dc63059)

(cherry picked from commit b2b78fd6)

(cherry picked from commit b47fdf9b

)

Co-authored-by: Jerry Zhao <jerryz123@berkeley.edu>

Remove vsim/emulator flows, add simple make verilog flow (backport #3494)

Remove SCIE interface (backport #3499)

* Remove vsim/emulator flows, add simple make verilog flowx

* Remove unnecessary dependencies from Makefile'

(cherry picked from commit 4a1715eb)

(cherry picked from commit d4775722)

Connect all s1_data fields in SimpleHellaIF (backport #3497)

Fix Makefrag for mill cross-compile (backport #3489)

Make StoreGen support narrow typ field (copy #3479)

Suppress SourceShrinker require if no shrinking is to be done (copy #3485)

(cherry picked from commit 1d69e6db)

(cherry picked from commit ec106af4)

This makes it a bit easier to use the StoreGen circuit. StoreGen shouldn't error if the `typ` argument is narrower than `maxSize` would normally permit.

(cherry picked from commit 9a416a16)

(cherry picked from commit a8663bc0)

Sync master with dev

Fixes for latest chisel

add WithScratchpadsBaseAddress to alter rocket core dtim address

fix PLIC 0-bit connection