These are faster and small don't cost much more.

Cleanup some register primitives

jtag_vpi: add some hysteresis for waiting for init_done

shiftReg: Make it so that register '0' is always closest to the q output, regardless of the type of shift register created.

Add explicit toBool cast on reset, for chisel3 compatability

Add a FrontBus to which low-bandwidth bus masters attach

There is a buffer on the sbus backside.
There is a buffer on the pbus frontside.

Between them is only an AtomicAutomata.
That should be enough for most designs.