fpga-zynq is now deprecated, move reference to sifive/freedom.

src/main/scala/rocketchip/Configs.scala should be src/main/scala/subsystem/Configs.scala now

* Added emulator debugging with GDB documentation

This documents the process of debugging RISC-V programs against the GNU debugger with OpenOCD.
https://github.com/freechipsproject/rocket-chip/issues/1339

* Review 1 by Megan.

review 1

* The executable arg is a dummy arg when using RBB emulator

* testing programs on emulator + reducing size ideas

+ Pointed out that {more size --> more execution time} and a solution.
+ Separated simple programs execution and testing (step 2) of program debugging (step 3): To illustrate the fact that custom programs can be run on the emulator too not only the benchmarks.

* typo minor change

* Modifications

Added an example command of VCD output + log file generation
Rearranged VCD size idea into the part where I talk about executing/testing
Cleaned redundancies

* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC

also update list of files expected to be seen in generated-src

* Refactors package hierarchy.

Additionally:
  - Removes legacy ground tests and configs
  - Removes legacy bus protocol implementations
  - Removes NTiles
  - Adds devices package
  - Adds more functions to util package

As pointed out, if we just point to 'master' branch, then people wouldn't get the correct list of dependencies.

Tell people where to look to find package dependency information

Make it easier to build riscv-tools faster on multicore machines

As per https://github.com/ucb-bar/rocket-chip/pull/507

fixed torture link

Fixed path to Configs.scala

This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected).  However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary.  Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.

This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence.  The main blocker is the lack of Verilog parameterization for
BlackBox.  It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL.  But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.

- List things that are no longer submodules as subpackages instead
- clean up some formatting issues

Correct typo in heading

The SCR file is gone, too, because it was tightly coupled.  The
general concept could be revived as a module that somehow connects
to the debug module.

English major I'm not, but my sister was and she says 'who' is correct here

- Removed instruction to checkout riscv-tests (as they are now globally installed when building the riscv-tools).
- Clarified the riscv-tools set-up information to clarify that the rocket-chip/riscv-tools is the version to build.

Corrected PublicConfigs.scala -> Configs.scala

Streamline makefiles for more robust test dependency generation. Note: emulator/generated-src-debug no longer used

typo?