It takes a while for the pipeline to compute the stall signal, so avoid
using it until the last logic levels in the clock cycle.

Don't build verilog twice for emulator and emulator-debug

Fix I$ miss perfctr

Since we aren't using chisel2, the output is the same either way.

TLXbar: Allow more masters and slaves and issue a warning.

Closes #920

The old version was counting prefetches, too.

Icache prefetch

Fix some critical paths

TLFuzzer: Allow Ordered clients to be created as well by the fuzzer

diplomacy: Pretty Print for TransferSizes

This cuts an I$->D$ path.

tilelink: add mask rom

Fix D$ ready-valid signaling bug

Tilelink map

The cache can't sink a grant every cycle, so extra E buffering doesn't help.

I broke this in 66d06460.

add optional tile boundary buffers

Mitigate I$->D$->I$ critical path

dcache: break potential combinatorial loop

This seemingly irrelevant change shaves several gate delays off the I$
tl.a.valid path.

Fix D$ ready-valid signaling bug