Otherwise, we don't get coverage data from the simulator.

The SCR file is gone, too, because it was tightly coupled.  The
general concept could be revived as a module that somehow connects
to the debug module.

Until now, the number of L1 client channels was set statically in the
configuration. This static configuration also assumed the same number of
cached and uncached channels per tile. As we plan to move towards
heterogenous multicore systems, this restriction should be removed.

This commit changes the generator so that number of channels per tile
can be independently set (using cde.Parameters.alterPartial).
The OuterMemorySystem will dynamically compute the number of cached and
uncached channels by summing the number of each kind of channel per core.

These failed for Andrew earlier.  While it might be paranioa, there's
really no reason to build the man pages so we might as well not bother.

Default to Chisel 3

Now that we can test Chisel 3 on Travis, I think it's time to turn it on
for everyone else.

Now that we have verilator support we can start testing the Chisel 3
Verilog on Travis.  This disables Chisel 2 Travis tests because they're
too slow.