- Jul 07, 2016
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Howard Mao authored
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Andrew Waterman authored
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- Jul 06, 2016
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Howard Mao authored
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Howard Mao authored
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- Jul 02, 2016
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Howard Mao authored
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Howard Mao authored
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Howard Mao authored
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- Jul 01, 2016
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Howard Mao authored
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- Jun 29, 2016
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Howard Mao authored
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Howard Mao authored
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Howard Mao authored
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Howard Mao authored
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Andrew Waterman authored
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Howard Mao authored
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- Jun 28, 2016
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Andrew Waterman authored
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Howard Mao authored
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Howard Mao authored
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- Jun 25, 2016
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Howard Mao authored
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Howard Mao authored
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- Jun 24, 2016
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Andrew Waterman authored
Otherwise, we don't get coverage data from the simulator.
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Howard Mao authored
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Andrew Waterman authored
The SCR file is gone, too, because it was tightly coupled. The general concept could be revived as a module that somehow connects to the debug module.
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Andrew Waterman authored
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- Jun 23, 2016
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Andrew Waterman authored
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Howard Mao authored
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Howard Mao authored
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Howard Mao authored
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Howard Mao authored
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Howard Mao authored
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Howard Mao authored
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- Jun 22, 2016
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Howard Mao authored
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- Jun 21, 2016
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Howard Mao authored
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Howard Mao authored
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Howard Mao authored
Until now, the number of L1 client channels was set statically in the configuration. This static configuration also assumed the same number of cached and uncached channels per tile. As we plan to move towards heterogenous multicore systems, this restriction should be removed. This commit changes the generator so that number of channels per tile can be independently set (using cde.Parameters.alterPartial). The OuterMemorySystem will dynamically compute the number of cached and uncached channels by summing the number of each kind of channel per core.
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- Jun 18, 2016
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Andrew Waterman authored
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- Jun 17, 2016
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Palmer Dabbelt authored
These failed for Andrew earlier. While it might be paranioa, there's really no reason to build the man pages so we might as well not bother.
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- Jun 16, 2016
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Colin Schmidt authored
Default to Chisel 3
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Palmer Dabbelt authored
Now that we can test Chisel 3 on Travis, I think it's time to turn it on for everyone else.
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Palmer Dabbelt authored
Now that we have verilator support we can start testing the Chisel 3 Verilog on Travis. This disables Chisel 2 Travis tests because they're too slow.
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- Jun 15, 2016
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Palmer Dabbelt authored
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