This only affects cores that are capable of taking two interrupts on
back-to-back cycles, i.e., not Rocket.

More IP-XACT-like RegFieldDesc

Revert "Debug: don't need to fully populate flags array"

This reverts commit 197699b9.

instead of applying the same description to the registers that it doesn't
actually do anything with (the padding registers)

Update TestDriver module to support FSDB

util: use chisel3.core.dontTouch

sbt: bump json4s-jackson to 3.5.3

The riscv-fesvr submodule was pointing at my local version, oops. This
corrects that in an updated version of riscv-tools.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Add +permissive/+permissive-off for VCS args

This adds guards around Verilog/VCS options for VCS calls with HTIF's
new `+permissive`/`+permissive-off` options. This enables HTIF to
permissively parse all options inside one of these guards while not
erroring on unknonw commands. This is necessary for VCS, unlike with the
emulator, as HTIF is giving all commands as opposed to only host and
target arguments (like with Verilator/emulator.cc).

* Bump riscv-tools for fesvr VCS fix

* Bump riscv-rools/riscv-fesvr (VCS stderr fix)

Fixes #1266

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Deprecate JTAGVPI

Also brings in an autoclonetype enhancement and some bug fixes

- Aligns RoCC with #1232.
- Fixes #1268.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Add BusErrorUnit RegFieldDesc

SimJTAG: make the reset/init connectivity more flexible.

PLIC: Update RegFieldDesc:  source 0 is different