For determinism and X tolerance.

Will help with timing for [pseudo-]LRU.

perSet returns true if the policy's state is typically replicated
for each cache set (as with LRU) or is typically global (as with
Random).  It's not binding, but it's useful for cache controllers.

Public accessors for SRAM modules

Update to Chisel 3.4.0 and FIRRTL 1.4.0

Use sbt-sriracha for fully SBT-managed source dependencies. They are
also toggleable via JVM System Properties: sbt.sourcemode and
sbt.workspace.

Update Makefiles and build rocketchip fat jar.

Support switching between source and published chisel3 and firrtl, test
in CI. Document this flow for bumping and describe impact of this flow
on IDE use.

Enable ProcedureSyntax lint rule

Enable LeakingImplicitClassVal lint rule

We cannot use '<>' due to the usual chisel3 bug with both sides wires.
To appease ':<>', the types must be identical, so we need a cast.

Add scalafix and remove unused imports

Support subbanking the D$ to save power for narrow accesses

This is particularly useful for reducing energy per scalar access
when attaching a coprocessor that requires a very wide D$ port.

AXI4Deinterleaver: add a buffer when optimized away

subsystem: update InterruptBusWrapper crossing code

Otherwise, cycle timing of the design can be impacted by the optimization
which removes this IP. The new default changes the behaviour to leave the
timing unaffected by the optimization, which, while a change, is safer.

Relax master parameter of RocketCrossingParams

bug fix for inlined xbar