floatTypes should be a def, otherwise minFLen/fLen may be 0 when the expression is evaluated

On systems without atomics a dummy bundle is created.
After switching to chisel3 the explicit tieoff is required to prevent an
unconnected wire error during verilog generation.

* [fix] missing PTE Cache tag MSB caused by width mismatch

* consider tag is wider case

* Update src/main/scala/rocket/PTW.scala

Co-authored-by: John Ingalls <43973001+ingallsj@users.noreply.github.com>

Co-authored-by: John Ingalls <43973001+ingallsj@users.noreply.github.com>

* feat: convert groundtest to chisel3 (#3048)
* refactor util/package to chisel3. (#3050)
* refactor TLBPermissions to chisel3. (#3055)
* refactor ICache to chisel3. (#3064)
* refactor PTW to chisel3. (#3067)
* refactor CSR to chisel3. (#3068)
* refactor Timer to chisel3. (#3078)
* refactor DCache to chisel3. (#3077)

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>
Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: SingularityKChen <chency_singularity@163.com>

+ also remove "init = " and "next = " (with param name) as new chisel-plugin in 3.6 won't compile.
+ DontCare the IO as there are some unconnected IOs in some occasions.

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

* refactor IBuf to chisel3.

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

convert prci directory to use chisel3

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* feat: convert unittest to chisel3

Convert unittest subdir to use chisel3

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

- Converts the regmapper directory to chisel3
- fix import style and add IO wrapper
- Add IO wrapper for declaration, and use explicit import
- remove whitespaces and brackets

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

Bump the formal subdirectory to chisel3

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>

* Add TLResourceRemover

* RegionReplicator: only check prefix when relevant

* Support incoherent access to AXI4 extmem through sbus

RoccBlackBox fixes for: 1) incorrect signal assigned to rocc_resp_bits_rd; 2) incorrect behavior in synthesis result (tested on FPGA) (#3035)

Removed TraceGen in HeterogeneousTileExampleConfig

Convert toaxe.py to Python3