Add Debug tests to Regressions

Make more use of chisel3.experimental.DontTouch

In accordance with https://github.com/freechipsproject/chisel3/issues/752

Allow rwReg to pass name and description to RegField for documentation.

Fix TL MMIO port

Claim that ErrorDevice is TRACKED

This is because as of Dec 12, 2017, Travis changed their container images and seem
to give slightly less disk space. Using a sudo image gives more disk space.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

This clarifies and provides consistent for the command line arguments
usage text.

This adds a set of examples for running the rocket-chip emulator.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

This, with riscv-fesvr modifications, enables the rocket-chip emulator
to understand (and error out) if a command line argument that will
eventually be consumed by HTIF looks bad and can error out quickly.
This relies on modifications to risc-fesvr to support getopt and the
exposure of what HTIF arguments exist via the `htif.h` header.

This removes the necessary preprocessing of riscv-fesvr arguments to
avoid situations where riscv-fesvr thinks that an argument is the
binary. Support for this is rolled into riscv-fesvr.

debug: attempt to make the simulation deterministic by not returning until connection is made and command is receieved

Cleanups, and print out log names ASAP.

Factor out gdbserver common invocation into GDBSERVER (fixing
--print-failtures).
Add --print-log-names to that command so the logfiles can be inspected
while the simulation is still running.
`RISCV=... cmd` is more idiomatic than `export RISCV=... && cmd`

This is simpler than JTAGVPI and is supported better by Verilor.
It is also the same thing Spike uses.

...even though it still supports Acquire.  This avoids needing to flush
the D$ on FENCE.I because of the presence of the ErrorDevice.

Memory regions that are uncacheable or have get/put effects should not
reside in the D$, so there is no need to flush them.