Refactor BaseTile again (to obviate augmentedTileParameters)

Hardfloat used to require Chisel 2 for testing, which is only published
for Scala 2.11. Rocket uses Scala 2.12, which meant the build system
needed a workaround to make hardfloat use Scala 2.12 when being used as
a part of rocket.

Hardfloat's tests have been updated to use Chisel 3, so the workaround
is no longer needed. This commit bumps the hardfloat submodule and
cleans up build.sbt to use Scala 2.12 only and Makefrag to not use
++2.12.4.

Further fix per-line cache flushing

+ replace SharedMemoryTLEdge with TileVisibilityNodeKey
+ encapusulate Parameter augmentation within BaseTile
+ simplify tile input constants
+ provide some LookupByHartImpl impls
+ remove augmentedTileParams

Don't engage release state machine when release is outstanding

Partially revert 3f962e9a,
which was a hacky way of nacking the subsequent requests

For per-address cache flushing, don't evict same line twice

This doesn't actually affect any correct M-mode software, but
is technically necessary for spec compliance.

Conditionally depend on chisel
* By default, depend on subproject in directory "chisel3"
* If environment variable "ROCKET_USE_MAVEN" is defined, use maven dependency

* adding rangefilter to the getOMMemoryRegions gating expression

Permit execution past corrupt uncached D-responses

Object model: Make OMECC an OMEnum type

* adding Option[RegFieldDesc]

Make the mimpid CSR value a parameter

This isn't a bug fix, but will eventually help with powering off the cache.

Move FPU load pipeline register into ungated clock domain

This avoids having to clock the FPU during MMIO loads, right up until
the load comes back.

Increase the number of situations in which frontend can be clock gated

Add external global interrupts

The fetch queue needs to fill up, which currently is only possible with
certain code sequences.  This PR makes the fetch queue flow control exact
rather than conservative, removing the software constraint.

Bump firrtl

Summary of changes:
* Async Reset Register support
* Minor improvements to constant propagation and code generation
* Minor performance improvements
* Add "mverilog" compiler with minimal optimizations

Extend CoreMonitorBundle with Clocked trait.

* testing fix to correctly generate brams in vivado

* added case of no maskpid

* fixed typo