This also constant-propagates through the async crossing.

This is now legal, since it is a WARL register.

This commit reduces the amount of Verilog that gets generated by about
200 KB.  It should have no semantic impact.  (The regmapper uses explicit
base addresses for each field, so changing the size of the array doesn't
affect the generated memory map.)

Support non-power-of-2 data scratchpads

Memory system features