AsyncResetReg: remove mux that was introduced as a workaround

Speed up program loading via DTM

PLIC optimizations

There are no longer '0' registers which don't toggle.
There enable registers are grouped in multiplies of 8 to reduce line count.

This does not save as many lines as I'd like, because it expands the priority vector.
Thus, you get one line for the wire, assign, and instance arg passing.

This saves a bit of verilog complexity.

Bump riscv-tools

Annotate register field descriptions

Fix regressions introduced by #1362

It's not actually incorrect to retire an instruction while in WFI-mode.
The assertion was enforcing a particular uarch behavior, not the spec.