- Jul 30, 2017
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Donggyu Kim authored
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- Jun 03, 2017
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Donggyu Kim authored
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- May 27, 2017
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Donggyu Kim authored
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- May 18, 2017
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Donggyu Kim authored
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- May 11, 2017
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Donggyu Kim authored
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- May 09, 2017
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Christopher Celio authored
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Christopher Celio authored
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Christopher Celio authored
* Currently, Rocket's CSR uses retireWidth to set hpm events increment Width. * BOOM's configs must then set its desired PerfIncWidth. * Addresses rocket-chip/issues/733 (albiet, in a heavy-handed manner).
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- May 06, 2017
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Christopher Celio authored
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- May 05, 2017
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Christopher Celio authored
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- May 04, 2017
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Christopher Celio authored
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- Apr 30, 2017
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Christopher Celio authored
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Christopher Celio authored
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- Apr 18, 2017
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Donggyu Kim authored
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Donggyu Kim authored
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- Apr 08, 2017
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Christopher Celio authored
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Christopher Celio authored
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- Apr 01, 2017
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Donggyu Kim authored
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- Mar 31, 2017
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Donggyu Kim authored
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- Mar 30, 2017
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Donggyu Kim authored
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- Mar 29, 2017
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Donggyu Kim authored
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- Mar 27, 2017
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Christopher Celio authored
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- Mar 20, 2017
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Donggyu Kim authored
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Donggyu Kim authored
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- Mar 19, 2017
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Christopher Celio authored
- A BOOM core has its own TLB. Which needs a TL2 edge. And a PTW port. - Add edge implicit input to Core. - Widen CoreIO to accept a ptw_tlb port. - Modify RocketCoreParams to handle wider fetchWidths, retireWidths. - Hack PTW requestor count to accommodate extra PTW port. - Wire up PTW requestor to the core's TLB in the Tile.
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Christopher Celio authored
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- Mar 18, 2017
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Donggyu Kim authored
becase reqs can be invalidated
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- Mar 16, 2017
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Donggyu Kim authored
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- Mar 15, 2017
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Donggyu Kim authored
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- Mar 14, 2017
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Andrew Waterman authored
It's redundant with the new scheme, so just adds HW for no reason.
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Andrew Waterman authored
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Andrew Waterman authored
We were zero-extending it, which is a double-precision zero in the recoded format. So, when spilled and reloaded with fsd/fld, the original value was destroyed. Instead, set the MSBs so that it represents sNaN. When spilled, the single-precision number will be preserved as the NaN payload.
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- Feb 11, 2017
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Jacob Chang authored
Add externalIn and externalOut property to Nodes that indicates whether the edges are external or not. (#554)
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- Feb 10, 2017
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Henry Cook authored
Fundamental new features: * Added tile package: This package is intended to hold components re-usable across different types of tile. Will be the future location of TL2-RoCC accelerators and new diplomatic versions of intra-tile interfaces. * Adopted [ModuleName]Params convention: Code base was very inconsistent about what to name case classes that provide parameters to modules. Settled on calling them [ModuleName]Params to distinguish them from config.Parameters and config.Config. So far applied mostly only to case classes defined within rocket and tile. * Defined RocketTileParams: A nested case class containing case classes for all the components of a tile (L1 caches and core). Allows all such parameters to vary per-tile. * Defined RocketCoreParams: All the parameters that can be varied per-core. * Defined L1CacheParams: A trait defining the parameters common to L1 caches, made concrete in different derived case classes. * Defined RocketTilesKey: A sequence of RocketTi...
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Henry Cook authored
Update config override documentation
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Henry Cook authored
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Henry Cook authored
Fix up Absolute value.
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- Feb 09, 2017
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Edward Wang authored
As per https://github.com/ucb-bar/rocket-chip/pull/507
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Jim Lawson authored
As of ucb-bar/chisel#491 and 32885ac, abs now returns the same type as its argument. Add a cast to UInt.
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- Feb 05, 2017
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Wesley W. Terpstra authored
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