Correct link to diplomacy carvv paper.

Add IOHelper

#1969 accidentally reverted the fix implemented in #1934.

TLBs: make Entry classes available from other packages

Add feature-disable bit to suppress corrupt on GrantData

This isn't actually an RTL change, since Rocket unconditionally
provides the chicken CSR.

TLWidthWidget: one more fix for the port to chisel3

Improve D$ ECC timing

Temporarily suppressing corrupt GrantDatas facilitates using normal loads
and stores to wipe down uncorrectable errors.

Remove unused type parameter on RegisterRouter.

Convert some modules to Chisel3

The previous logic suppressed dirty-bit writes in the event of a data
error.  This is a good thing, because if the error had been uncorrectable,
and the line had been clean, we could just discard the line and refetch it,
rather than being forced to report an uncorrectable error.

Unfortunately, that logic creates a critical path from the data ECC check
to the tag RAM.  Instead, allow the dirty-bit write to proceed, but
then immediately victimize the line, so that the tag will be set to invalid.
The ultimate effect is the same as before.

A side effect of 46e0fcb481ef3b1fdd47bdae1b27e1b31e5e8d07 is that the cache
is guaranteed to enter the victimization state machine whenever this
scenario occurs (which is a requisite property to preserve the uncorrectable
error behavior).

* Bump chisel3 3.2.x for Select.instances bugfix

Co-authored-by: Deborah Soung <debs@sifive.com>

* clocks: copy clocks package from sifive.fpgashells; update imports

* clocks: bundles can use chisel3 bundle to get cloneType for free

* clocks: use chisel3 in all files

* clocks: add ClockSinkDomain and ClockSourceDomain

* clocks: allow for unspecified clock freqs

* clocks: add TestClockSource test harness clock generators

* clocks: domain nodes are named clockNode

* clocks: source and sink nodes offer fixedClockResources

* rename package from clocks to prci

* clocks: ClockGroup.pickGroupFromCrossingType

* prci: make abstract base ClockDomain class

* prci: add FixedClockBroadcastNode

* tilelink: add fixedClockOpt to HasTLBusParams

* tilelink: add clock nodes to TLBusWrapper

* subsystem: add clockGroupNode to BaseSubsystem

* devices: add example device that can gate clock from TL register-mapped interface

* prci: add draft of ClockDivider adapter

* buswrapper: derive dtsClk from clockNode.fixedClockResources

* util: update ClockDivider to chisel3

* prci: add package object to hold asyncMux helper func

* prci: add ClockGroupSourceNode and ClockGroupSinkNode

* prci: ClockGroup and ClockGroupBroadcast are LazyRawModuleImps

* prci: domain creates clock and reset output IOs

* prci: rename ClockGroupBroadcastNode to ClockGroupAggregateNode

* tilelink: TLBusWrapper includes ClockGroupAggregator

* tilelink: TLBusWrapper  crossTo/FromBus take implicit ClockGroupIdentityNode

* system: ExampleRocketSystem supplies default simple clock source

* subsystem: BaseSubsystem has ClockGroupIdentityNode

* prci: SimpleClockGroupSource can have a variable number of sources

* groundtest: subsystem needs dummyClockGroupSourceNode

* prci: add FixedClockBroadcast helper module and use in TLBusWrapper

* prci: ClockEphemeralNode and ClockGroupEphemeralNode

* prci: TLBusWrapper uses ClockGroupEphemeralNode

* subsystem: add traits HasAsyncClockGroupsNode and Attachable

* subsystem: clean up Attachable and add SubsystemDriveAsyncClockGroupsKey

* prci: add PRCIClockGroupNode: NexusNode(ClockGroupImp)

* tilelink: better name for BuwWrapper clock aggration nodes

* groundtest: delete import that was actually unused

* prci: move ClockGroupDriverParameters to prci

Debug SBA: Don't reset sbState if dmactive is set to 0

Correct spelling of TileLink in Object Model protocol description

Rocket Core DCache TileLink: require FIFO to allVolatile regions

GroundTestTileParams Some(ICacheParams)