+ Rename `given` to `allocated`, as `given` will become a keyword
  in Scala 3.

Also bump nix to add circt

Also update arch-test script to use new isa spec of toolchain
see https://lkml.org/lkml/2022/1/24/537

This was introduced by "(185cac83) Add hypervisor extension (#2841)"

This is a dead code, as no circuit is producing and consuming
this bit.

This was discovered when migrating Core.scala to chisel3, where
strict checking was applied for IO and firrtl found this is
not connected.

In the context of hypervisor extension, V bit, or _virtualization
mode_, indicates whether the hart is currently executing in a
guest.

For TLBReq, the V bit is needed as it affects the PTW thus TLB
behavior on whether to do _Two-Stage Address Translation_.

However, the bit is not needed for TLBException. The exceptions
(pf, gf, ae, ma) have no V=1/V=0 variants. Also, there is no point
to add V bit for gf (guest page fault).

The io.resp.gf added below in the original patch also does
not connect io.resp.gf.v. If this V bit should be added
for this specific exception, it should be connected.

I assume this was added accidentally, as the original
"extends CoreBundle()(p)" modification seems irrelevant.

This removes a redundant port
As rnum is encoded in rs2 as imm now,
we can get it just from rs2

It is not rs2, it is imm
Related to https://github.com/chipsalliance/rocket-chip/issues/3255

See 0b7fef44

Ref to
https://github.com/chipsalliance/firrtl/commit/7a4f15aa27aed8ce9cc180fb89126a954638e102

scala.reflect.internal.Types: constructor RecordMap in class RecordMap cannot be accessed in package util from package util in package rocketchip

Ref to https://github.com/chipsalliance/rocket-chip/pull/2889

Cherry-picked https://github.com/chipsalliance/chisel3/commit/7372c9e2eed082d35abbe55f856d03fda68dc0be
Should use BarrelShifter from chisel3.std, but it is not published,
see https://github.com/chipsalliance/chisel3/pull/2997

util: fix errors during FIRRTL pass

Assorted fixes for scala 2.13/chisel 3.5.5