We were using it to compute the next PC on flush vs. replay (which require
PC+4 and PC, respectively).  This fix gets rid of the adder altogether by
reusing the M-stage PC in the flush case, which by construction holds PC+4.

It was counting conflict misses but not cold misses.

Handle parity errors with a pipeline flush rather than a faster
frontend replay, reducing a critical path.

The deleted code was a holdover from Hwacha's vector fences.

It takes a while for the pipeline to compute the stall signal, so avoid
using it until the last logic levels in the clock cycle.

Don't build verilog twice for emulator and emulator-debug

Fix I$ miss perfctr

Since we aren't using chisel2, the output is the same either way.

TLXbar: Allow more masters and slaves and issue a warning.

Closes #920

The old version was counting prefetches, too.

Icache prefetch

Fix some critical paths

TLFuzzer: Allow Ordered clients to be created as well by the fuzzer

diplomacy: Pretty Print for TransferSizes

This cuts an I$->D$ path.

tilelink: add mask rom

Fix D$ ready-valid signaling bug

Tilelink map

The cache can't sink a grant every cycle, so extra E buffering doesn't help.

I broke this in 66d06460.