Co-authored-by: Jack Koenig <koenig@sifive.com>

Ref to https://github.com/chipsalliance/rocket-chip/pull/2889

Porting Chisel 2 to Chisel 3: tilelink/ (backport #3287)

+ using `DontCare`

(cherry picked from commit 5f7278b4)

+ in.d and out.a;

(cherry picked from commit e52773e8)

+ using `DontCare`

(cherry picked from commit 39024972)

(cherry picked from commit 6c231009)

Implement Zicond extension (backport #3329)

* Instructions: sync from riscv-opcodes (add zicond)

* Zicond: implement czero.eqz, czero.nez

* Zicond: fix implementation

* Zicond: reduce code duplication

* Add ISA extension when using Zicond

* Fix ISA extensions ordering

(cherry picked from commit 62162c5e)

* Add API to force TLBuffers into RocketTile as boundaryBuffers

* Generate boundaryBuffers within the Tile, not the TilePRCIDomain

(cherry picked from commit 3f74d79b

)

Co-authored-by: Jerry Zhao <jerryz123@berkeley.edu>

Enables filtering out multiple ranges at once.

(cherry picked from commit 41105631

)

Co-authored-by: Jerry Zhao <jerryz123@berkeley.edu>

In legacy code it is ok to clone a Wire using Wire()
now the requirement is more strict and WireDefault is needed

Related to #3059

The Output is added for code style consistency

Closes #3324

(cherry picked from commit fb5d7d0f

)

Co-authored-by: Zenithal <i@zenithal.me>

(cherry picked from commit 2570db7c

)

Co-authored-by: Jerry Zhao <jerryz123@berkeley.edu>

(cherry picked from commit 58c82498

)

Co-authored-by: Yangyu Chen <cyy@cyyself.name>

Fix no-debug-node designs (backport #3322)

(cherry picked from commit 3b8d3c16)

Support overriding the device set for diplomatic SRAMs (backport #3320)

(cherry picked from commit c8edec39)

(cherry picked from commit 12e21a61)

Porting Chisel 2 to Chisel 3: devices/ (backport #3278)

Porting Chisel 2 to Chisel 3: rocket/ (backport #3282)

Porting Chisel 2 to Chisel 3: amba/axi4/UserYanker.scala (backport #3277)

Fix CharCount RoCC example bug (backport #3305)

Change CharCountRoCC Example to use dcacheParams (backport #3304)

Hypervisor: encodeVirtualAddress extra MSB to canonicalize VS-disabled (backport #3314)

(cherry picked from commit 0504a9b8)

riscv-tests.suite[] wont compile

(cherry picked from commit d86c011d)

RoCC accesses D$, not I$

(cherry picked from commit 61ea81c1)

Reset recv_beat

(cherry picked from commit f19a90af)

L1TLB: VS-mode SFENCE misses tera/giga-page entries fragmented superpages (backport #3297)