* coreplex collapse: peripherals now in coreplex

* coreplex: better factoring of TLBusWrapper attachement points

* diplomacy: allow monitorless :*= and :=*

* rocket: don't connect monitors to tile tim slave ports

* rename chip package to system

* coreplex: only sbus has a splitter

* TLFragmenter: Continuing my spot battles on requires without explanatory strings

* pbus: toFixedWidthSingleBeatSlave

* tilelink: more verbose requires

* use the new system package for regression

* sbus: add more explicit FIFO attachment points

* delete leftover top-level utils

* cleanup ResetVector and RTC

tileink: FIFOFixer should cope with zero-latency devices

ShiftQueue: support constant propagation

also update list of files expected to be seen in generated-src

PLIC: Add maxPri as well as ndev in DTS

Rename offchip-interrupts to external-interrupts.

BootROM parameters currently control the boot rom address, size, and the
hang which essentially sets the reset vector. This commit allows specifying
different parameter values as required.

I used the singular because there is really only one max priority

In particular, it is ok if no slaves actually need FIFO fixing.
It is also ok if none of those fixed are FIFO.

Fifo fixer configable

regfield: More explanatory requires so I don't have to RTFC and figure out what width actually was (#855)

Use chisel3 Clock() method.

SRAM errors