Skip to content
GitLab
Commit 528deefd authored by pbing's avatar pbing Committed by Andrew Waterman
Browse files

Change SystemVerilog statement into standard Verilog (#997)

parent c24b275f
Hide whitespace changes
Inline Side-by-side
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment