D$: support specifying the cache index when aliasing possible

Since the same physical address can legally live in multiple places for
caches that support aliasing, we can expose this additional degree of
freedom. It is useful for decoupled accelerators whose memory addresses
have been converted up front.  If they use the physical address directly,
then they'll often access the wrong set, causing an aliasing miss.  If
they happen to know which alias is most likely, they can use this new
mechanism to choose it.

No change for the non-aliasing case.