fixes arguments passed to vcs-/verilator-based simulators

Adds the "+permissive/+permissive-off" options to the vcs-based simulator
which matches the changes in riscv-fesvr. Also, fixes the order of the
arguments passed to the simulators.

Closes #13
Closes #14

Use https:// for riscv-test-env submodule.

Also point to the new repo URL, under the riscv/ org.

Added loop option and loop size into configs

Also, split original loop config into loop and segments to decide whether to loop and have
multiple psegs or loop and have one pseg

This can't be fetched from travis.

   - to get a waveform dump use "-dump" flag (not -dc or -dv),
      OR set torture.testrun.dump to true in config file
   - ONLY dump a waveform if a mismatch occurs ("debug" gets set to true).
   - on a test mismatch, do NOT re-run using $RTL_CONFIG-debug
      (This leads to confusing behavior and is running the test on a different
      circuit!).

closes #1.

   closes #2

   - moved source code into their respective */src/main/scala
     directories.

+hopefully this fixes torture inexplicably hanging during spike-dasm
sometimes