add Probebuff

Update dtm.h with switch_to_* functions

Signed-off-by: Abraham Gonzalez <abe.j.gonza@gmail.com>

Fix behavior of unavailable harts.

Change disasm for vset{i}vli with reserved vtypes to display the reserved bits

Currently there is a bug with the disassembly when vsetivli/vsetvli have invalid vtypes (with reserved bits set). Spike correctly detects this and sets vill, but the disassembler integrated into spike ignores those bits being set and prints the instruction as if they weren't. This makes debugging harder, it looks like an otherwise valid vtype was being rejected and can lead down debugging paths like thinking the vector unit is configured incorrectly.

This commit changes the behaviour so that if these reserved bits are set, it prints out the hex value of the vtype. This is understood by the assembler.
GCC disassembler prints out the decimal value of the vtype in this case, I think that hex value is clearer but I can change it if desired.

Signed-off-by: Brendan Sweeney <brs@eecs.berkeley.edu>

Hit multiple icount triggers with different actions

triggers: refactor: icount: breakdown detect_icount_match() into detect_icount_fire() and detect_icount_decrement()

Attempt to fix Mac OS CI

Signed-off-by: viktoryou <143797577+viktoryou@users.noreply.github.com>

fix bf16 nanboxed access 

 assume
    0x0000_0000_0000_7d2d at 0x8000_0000
    a0 = 0x8000_0000

    fld ft0, 0(a0)           <-  load 0x0000_0000_0000_7d2d to ft0,
                                 it is invalid Nanboxed

    fcvt.s.bf16  ft1, ft0    <-  read bf16 from ft0.  it should be
                                 0x7fc0 (bf16 QNaN) but not 0x7e00 (f16 QNaN)

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

 update model_test.h: set_msw/clear_msw/set_mtimer/clear_mtimer

fdt: Install header files `fdt.h` and `libfdt_env.h` as needed by `libfdt.h`

Include cerrno in fesvr/elfloader.cc

It caused compile error "use of undeclared identifier 'errno'" at line 26 and 33.
I Add #include <cerrno> in fesvr/elfloader.cc to fix error and compile successfully.

Rename *envcfg.HADE to *envcfg.ADUE

update set_msw/clear_msw/set_mtimer/clear_mtimer

Added ifndef to clint addresses instead of hard-coding
Added clear_msw and clear mtimer
Tested against Sail/isa-sim with new proposed Smclint/Ssclint arch-tests
https://github.com/riscv-non-isa/riscv-arch-test/pull/372


Building a baseline of interrupt tests that changes to SAIL/isa-sim can be tested against when other interrupt extensions are added.

Signed-off-by: Dan Smathers <dan.smathers@seagate.com>

triggers: fix textra.sbytemask

Add Smcntrpmf support

If Smcntrpmf is enabled, mcycle / minstret increment only if counting
for the privilege level isn't inhibited in mcyclecfg / minstretcfg.

This tracks whether the privilege / virtual mode was changed by the
execution of the current instruction.

Ignore corresponding bytes to the scontext and textra.svalue.
Cast 0xff to reg_t for the 34-bit textra64.svalue.

Add Smcsrind / Sscsrind support