spi: put a request buffer infront of SPI

This will prevent SPI from blocking other pbus requests.

Updates to go with the fpga-shells directory

mockaon: Adds logic to detect external rtc toggles

spi: Fix invalid D channel response when flash interface is disabled

Issue: When the memory-mapped flash region is accessed while the flash
read mode is disabled (fctrl.en flag is clear), the SPI flash controller
generates an invalid response on the D channel.
This may cause the TileLink bus to deadlock.

Workaround: Software should avoid accessing the memory-mapped flash
region when the SPI controller is not in the flash read mode.

Seperate GPIO Peripheral Functionality

* periphery: peripherals now in coreplex

* use fromAsyncFIFOMaster

and seperate out some of the "GPIO Peripheral" from "Pin Control"

1 - Print AXI-ID mappings
2 - Use half as many Deinterleaver buffers for the L2 backside
3 - Limit the Q depth on the PCIe control port to 2 (was 1584!)

* gpio: Make IOF optional

* IOF: Make the default false