- Jun 08, 2020
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Megan Wachs authored
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- Jun 02, 2020
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Megan Wachs authored
TLSPIFlash: correct OM register map generation code
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Megan Wachs authored
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- May 29, 2020
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Ryan Macdonald authored
Support for configurable hierarchies
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Ryan Macdonald authored
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Ryan Macdonald authored
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- May 28, 2020
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Ryan Macdonald authored
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Ryan Macdonald authored
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Ryan Macdonald authored
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Ryan Macdonald authored
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- May 27, 2020
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Ryan Macdonald authored
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Ryan Macdonald authored
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Ryan Macdonald authored
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Ryan Macdonald authored
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Ryan Macdonald authored
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- May 22, 2020
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Ryan Macdonald authored
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- May 21, 2020
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Ryan Macdonald authored
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- May 06, 2020
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Henry Cook authored
Convert toBool(s) to asBool(s)
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Henry Cook authored
Set PeripheryKey defaults to Nil
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- May 05, 2020
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Wesley W. Terpstra authored
This broke tests in a larger repository. This changed came in PR #141, but do not seem necessary.
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- Apr 30, 2020
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John Ingalls authored
IntSyncCrossingSink -> IntSyncAsyncCrossingSink
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- Apr 29, 2020
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Wesley W. Terpstra authored
Nothing seems to depend on this type bound.
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- Apr 14, 2020
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Kritik Bhimani authored
adds support for uart 4-wire mode operation and parity generation/checking
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Wesley W. Terpstra authored
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- Apr 13, 2020
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kritik bhimani authored
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- Apr 09, 2020
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kritik bhimani authored
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kritik bhimani authored
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kritik bhimani authored
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kritik bhimani authored
[uart] given any data written to TXDATA register now on it will consume only configured databits for parity calculation previously the assumption was to transmit 0x12 user will write 0x12 and not 0x112 in 8bit data mode
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kritik bhimani authored
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kritik bhimani authored
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kritik bhimani authored
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kritik bhimani authored
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kritik bhimani authored
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kritik bhimani authored
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kritik bhimani authored
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kritik bhimani authored
since it will be very rarely used it is added as a configuration time feature
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kritik bhimani authored
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kritik bhimani authored
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kritik bhimani authored
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