This refactors the receiver logic to compensate for the case of the baud
rate divisor not being multiple of the oversampling period.

Previously, the bit time was effectively rounded to (s * floor(div / s))
cycles, where "s" is the oversampling factor - the number of
intermediate samples for each data bit.  The remainder r = (div % s) was
ignored, thereby resulting in gradually accumulated drift that became
significant for divisor values on the same order of magnitude as "s".

The revised approach inserts the required additional delay by extending
the last "r" samples of a given data bit by one cycle each.

GPIO: IOF should not override PUE and DS

pinctrl: Add the ability to convert EnhancedPin to BasePin

PWM: Add the ability to invert the output directly in PWM

Create Signal Bundles vs just Pins

remove duplicate ResetCatchAndSync definition

spi: put a request buffer infront of SPI

This will prevent SPI from blocking other pbus requests.

Updates to go with the fpga-shells directory

mockaon: Adds logic to detect external rtc toggles

spi: Fix invalid D channel response when flash interface is disabled

Issue: When the memory-mapped flash region is accessed while the flash
read mode is disabled (fctrl.en flag is clear), the SPI flash controller
generates an invalid response on the D channel.
This may cause the TileLink bus to deadlock.

Workaround: Software should avoid accessing the memory-mapped flash
region when the SPI controller is not in the flash read mode.