- Feb 10, 2017
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Alex Solomatnikov authored
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Alex Solomatnikov authored
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Alex Solomatnikov authored
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- Feb 08, 2017
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Alex Solomatnikov authored
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Alex Solomatnikov authored
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- Feb 07, 2017
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Alex Solomatnikov authored
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- Feb 04, 2017
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Wesley W. Terpstra authored
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Alex Solomatnikov authored
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Alex Solomatnikov authored
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- Feb 02, 2017
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Wesley W. Terpstra authored
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- Feb 01, 2017
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Alex Solomatnikov authored
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Wesley W. Terpstra authored
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- Jan 31, 2017
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Wesley W. Terpstra authored
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- Jan 25, 2017
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Alex Solomatnikov authored
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- Jan 21, 2017
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Wesley W. Terpstra authored
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- Jan 20, 2017
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Wesley W. Terpstra authored
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- Dec 08, 2016
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Wesley W. Terpstra authored
This tracks PR #478 in rocketchip.
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- Dec 07, 2016
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Wesley W. Terpstra authored
This bug amazingly compiled correctly and ran correctly! It was saved by the AXIFragmenter which turned the "narrow burst" into individual beats that then got converted to 64b in TileLink land via inspection of the mask bits. The consequence is that AXI bus mastering proceeded at one word per DDR round-trip. Now it is one cache line per DDR round-trip. When we get L2 back in the design, it should really fly!
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- Dec 03, 2016
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Wesley W. Terpstra authored
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- Dec 01, 2016
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Richard Xia authored
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- Nov 29, 2016
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SiFive authored
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