1 - Print AXI-ID mappings
2 - Use half as many Deinterleaver buffers for the L2 backside
3 - Limit the Q depth on the PCIe control port to 2 (was 1584!)

* gpio: Make IOF optional

* IOF: Make the default false

periphery: convert bundle traits 

UART: actually return the pins, not just the module. We should do this for the other peripherals as well

GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they are more useful.

GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they are more useful.

Make more peripherals "listable" to allow for 0 or more

Async PCIe

This makes it possible to also drive a PLL of our own from the crystal.

This makes placement of the L2 and DDR controller easier.

axi4: switch to new pipelined converters

SPI errata fixes

Issue: Configuring the frame length to certain values causes incorrect
operation.

Symptoms: Certain frame lengths result in the master sending one extra
clock pulse.  The slave device may then become desynchronized.

Workaround: The following frame lengths are supported and can be used.
Do not use other frame lengths.
	* Serial mode: 0, 2, 4, 6, 8
	* Dual mode:   0, 1, 3, 5, 7, 8
	* Quad mode:   0, 1, 2, 3, 5, 6, 7, 8

Issue: The output enable signal for DQ[3] is not driven properly.

Symptoms: Output data from master to slave is not properly transmitted
in quad mode.  Data received from the slave is unaffected.

Workaround: When interfacing with SPI flash devices, do not use the
"Quad Input/Output Fast Read" command (opcode 0xEB) while in the
Extended SPI protocol.  Do not use the Native Quad SPI protocol.

Use _chisel3 analog for MIG inout

MockAON: Accept the non-debug interrupt as an input to overall reset.

Debug v013

Mux1H converts aggregates to UInt, muxes, then converts back which can
look like a cominational loop.