Convert toBool(s) to asBool(s)

Set PeripheryKey defaults to Nil

This broke tests in a larger repository.
This changed came in PR #141, but do not seem necessary.

IntSyncCrossingSink -> IntSyncAsyncCrossingSink

Nothing seems to depend on this type bound.

adds support for uart 4-wire mode operation and parity generation/checking

[uart] given any data written to TXDATA register now on it will consume only configured databits for parity calculation
previously the assumption was to transmit 0x12 user will write 0x12 and not 0x112 in 8bit data mode

 since it will be very rarely used it is added as a
 configuration time feature

Add CanHaveDevices; Util.scala -> Devices.scala

Rename attach->locate