Correct a few typos

ChipLink StuckSnooper

Correct name of rxen field

* Stream: Clean up register descriptions and groupings

* Clean up linebreaks and parentheses for readability.

Allow optional bus blockers to be inserted while attaching devices

* Improve SPI flash ffmt register layout and fix some field names

* SPI: use automatic Reserved RegField

* SPI: Correct description for ffmt register

* SPI/UART: fix FIFO descriptions.

* SPIFlash: keep registers in ffmt group, but use different calls to preserve alignment

FU-1204 pass-through active-high/low interrupt enable

* spi phase - coarse and fine grain - addition changes

* black box file for fine delay

* updates based on review

* fixed unintentional edit

* removed foundry specific cells and their references from the logic

* added centralized configurable delays

* Updates per review of the PR

* more review related updates

* review updates

* updates from review

* Fix fpga build issue

* SPI speedup changes to work in the corner condition when divisor is set to 0

* Updates per review feedback

subsystem: sbus.control_bus => cbus

Revert "Spi speedup - fine and coarse grain phase difference addition"

This reverts commit a0da03f5.

* spi phase - coarse and fine grain - addition changes

* black box file for fine delay

* updates based on review

* fixed unintentional edit

* removed foundry specific cells and their references from the logic

* added centralized configurable delays

* Updates per review of the PR

* more review related updates

* review updates

* updates from review

* Fix fpga build issue

Chiplink probe bypass