fix incorrect connection for input pin

GPIO: split function I/O bundle from GPIO bundle

Added power on reset genertor device

add additional GPIO pin connections

SPI ie Port

dq.ie := ~dq.oe

update the regfield name/description for csdef in spi

disable output enable of pin during dummy cycles for certain flash

Add HasDFT, CanHaveDFT Trait

trait HasDFT[T <: Data] -> HasDeviceDFTPorts[T <: Bundle]

HasDADft / HasJTAGDft -> HasDFT
dftDANode / dftJTAGNode -> dftNode

At the IP Onbrading
	1. Mixin HasDFT Trait
	2. Declare val dftNode as a bundle of ports to be used as DFT

Add GitHub actions

Trait HasDADft:
        dftDANode = Source Node for DA DFT
        makeDADftPort = Make Direct Access Port for DFT

Trait HasJTAGDft:
        dftJTAGNode = Source Node for JTAG DFT
        makeJTAGDftPort = Make JTAG Port for DFT

DevicesSubsystem: Temporarily get rid of DevicesSubsystemParams

TileLink Diplomacy parameters supportsProbe -> supports.probe