Fix mistake in changelog

Fix sip::{set,clear}_ssoft

`riscv-rt`: `_pre_init_trap` and weak symbols

`riscv-rt`: move all the assembly code to `asm.rs`

Cargo metadata for riscv-peripheral

Release new `riscv-peripheral` crate and minor patches

Make fence operations safe

`riscv-rt`: Fix nightly builds

Add `riscv-peripheral` crate

`sfence.vma`, `fence` and `fence.i` just add ordering constraints
load/store operations (between themselves, or other kinds of memory
access). There's no risk of any UB or other unexpected visible changes
in machine state, so we can make these "safe".

Publish latest riscv-rt patch on crates.io

Avoid spurious errors from LLVM

Release new versions