`riscv-semihosting`: bug fixes

Co-authored-by: Taiki Endo <te316e89@gmail.com>

add `riscv-semihosting`

`riscv`: ECALL and nested interrupts

`riscv`: support for S-mode

`riscv-rt`: Implement FPU initialization

`riscv-rt`: clean linker script

`riscv-rt`: Rework on exception and interrupt handling

- Replace fmvp.d.x usage with fcvt.d.w as it does not require zfa

riscv-pac crate

This reverts commit 41c50dd4.

`riscv-rt`: remove riscv-target ;`riscv`:update for embedded-hal to 1.0.0-rc.2