Rust nightly has started generating this section for RISC-V executables,
place it at the start of the bss area.

31: New linker script and multi-core support r=laanwj a=Disasm

* Linker script was reworked. Now it uses region aliases to relocate sections. This approach makes it possible to build firmware for both FLASH+RAM and RAM-only targets. Memory definitions now supposed to be present in their corresponding crates (e.g. RAM definition in PAC crate, FLASH definition in board support crate).
* Multi-core support was introduced. Cores are parked with `_mp_hook` function and then awakened in platform-dependent way.
* Documentation was updated to reflect new features.
* New crate version: 0.6.0

Depends on: https://github.com/rust-embedded/riscv/pull/28
Closes: https://github.com/rust-embedded/riscv-rt/issues/26



Co-authored-by: Vadim Kaushan <admin@disasm.info>

32: Rename RISCV to RISC-V r=laanwj a=Disasm

The same as here: https://github.com/rust-embedded/riscv/pull/25



Co-authored-by: Vadim Kaushan <admin@disasm.info>

This reverts commit 373d7737.

30: Fix docs, add MSRV policy, bump version r=dvc94ch a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

27: Add 'entry' and 'pre_init' attributes r=dvc94ch a=Disasm

Implementation is based on [`cortex-m-rt-macros`](https://github.com/rust-embedded/cortex-m-rt/tree/master/macros) code.

This implementation has been changed to make `static mut` unsafe inside entry point and different handlers.

Related: https://github.com/rust-embedded/riscv-rt/pull/20



Co-authored-by: Vadim Kaushan <admin@disasm.info>