`riscv-rt`: Rework on exception and interrupt handling

riscv-pac crate

This reverts commit 41c50dd4.

`riscv-rt`: remove riscv-target ;`riscv`:update for embedded-hal to 1.0.0-rc.2

embedded-hal 1.0.0-rc.2 introduces backwards incompatible changes.  This change pins the crate to 1.0.0-rc.1.

Add riscv-rt to workspace

Transition to cargo workspace

build.rs now adapts link.x for the target arch

Ensure sp is 16-byte aligned

Signed-off-by: Chien Wong <m@xv97.com>

Fix setting incorrect sp if single-hart

Signed-off-by: Chien Wong <m@xv97.com>

Signed-off-by: Chien Wong <m@xv97.com>

If single-hart is enabled, the sp is set to _stack_start - _hart_stack_size,
rather than _stack_start. Fix this.

Fixes: e540f1e4

 ("Add feature single-hart")
Signed-off-by: Chien Wong <m@xv97.com>

Ignore hartid in single-hart mode.