`sfence.vma`, `fence` and `fence.i` just add ordering constraints
load/store operations (between themselves, or other kinds of memory
access). There's no risk of any UB or other unexpected visible changes
in machine state, so we can make these "safe".

Publish latest riscv-rt patch on crates.io

Avoid spurious errors from LLVM

Release new versions

lib: update dependency embedded-hal to 1.0.0

Signed-off-by: jakezhu9 <zjx1319@hust.edu.cn>

`riscv-rt`: add links to Cargo.toml

`riscv-semihosting`: bug fixes

Co-authored-by: Taiki Endo <te316e89@gmail.com>

add `riscv-semihosting`

`riscv`: ECALL and nested interrupts

`riscv`: support for S-mode

`riscv-rt`: Implement FPU initialization

`riscv-rt`: clean linker script

`riscv-rt`: Rework on exception and interrupt handling

- Replace fmvp.d.x usage with fcvt.d.w as it does not require zfa