113: bump version to v0.9.0 due to breaking changes r=Disasm a=almindor

As per discussion on https://github.com/rust-embedded/riscv/pull/112

 we want to release `v0.9.0` and yank `v0.8.1` since the removals were a breaking change.

Co-authored-by: Ales Katona <ales@katona.me>

112: Propose to release a version `riscv` v0.8.1 r=almindor a=luojia65

The `riscv` crate includes an important fix (https://github.com/rust-embedded/riscv/pull/107

) where the RustSBI community would leverage the use of. However, the latest release v0.8.0 did not include this fix. In this pull request we want to propose to release a new version of `riscv` crate to include at least this fix, so that RustSBI community would write correct implemenations based on this crate.

Notes to `CHANGELOG.md`: the release date `2022-10-06` can always be changed.

r? `@Disasm` 

Co-authored-by: luojia65 <me@luojia.cc>

109: Update to edition 2021. r=Disasm a=Dirbaio

This shouldn't be a breaking change since Edition 2021 came out in
Rust 1.56, and MSRV is already higher than that (Rust 1.59)

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>

This shouldn't be a breaking change since Edition 2021 came out in
Rust 1.56, and MSRV is already higher than that (Rust 1.59)

108: fix: clearify that mip.{MSIP, MTIP} are read-only r=almindor a=luojia65

closes #62

In RISC-V privileged specification, it says:

> Bits mip.MTIP and mie.MTIE are the interrupt-pending and interrupt-enable bits for machine timer interrupts. MTIP is read-only in mip, and is cleared by writing to the memory-mapped machine-mode timer compare register.
>
> Bits mip.MSIP and mie.MSIE are the interrupt-pending and interrupt-enable bits for machine-level software interrupts. MSIP is read-only in mip, and is written by accesses to memory-mapped control registers, which are used by remote harts to provide machine-level interprocessor interrupts.

indicated by the specification, mip.MSIP and mip.MTIP bits are read-only. This pull request clearifies this by removing {set, clear}_{msoft, mtimer} functions from mip module of riscv crate.

Co-authored-by: luojia65 <me@luojia.cc>

closes #62

107: fix reading marchid and mimpid r=Disasm a=orangecms

It seems to have been a copy-paste error.
We ran into a very nasty bug in oreboot on the Allwinner D1 (C906) where
an errata patch in Linux relies on those two being zero.

Signed-off-by: Daniel Maslowski <info@orangecms.org>

Co-authored-by: Daniel Maslowski <info@orangecms.org>

It seems to have been a copy-paste error.
We ran into a very nasty bug in oreboot on the Allwinner D1 (C906) where
an errata patch in Linux relies on those two being zero.

Signed-off-by: Daniel Maslowski <info@orangecms.org>

105: Add extra documentation for `delay` r=almindor a=Joeyh021

Took me a minute or two to figure out what value exactly to pass to `McycleDelay::new`, so figured I'd make a quick PR to add a note for anyone else that hits the same confusion as I did. Also added a doc line for the `delay` module while I was at it, as it was missing one.

Co-authored-by: Joey Harrison <joeyh021@icloud.com>

104: Fix asm::delay not clobbering count register r=dkhayes117 a=adamgreig

I noticed that a small example using two `asm::delay()` calls worked fine in debug mode but not in release mode. Eventually `@jamesmunns` spotted that the count register wasn't being reloaded between calls:

```
    # loads a2 with real_cyc
    400001ce:	02faf637          lui	a2,0x2faf
    400001d2:	0816061b          addiw	a2,a2,129
    # turn on led
    400001d6:	c10c              sw	a1,0(a0)
    # count down (delay impl)
    400001d8:	167d              addi	a2,a2,-1
    400001da:	fe7d              bnez	a2,400001d8 <.LBB0_8+0x30>
    # turn off led
    400001dc:	00052023          sw	zero,0(a0) # 2000000 <.Lline_table_start0+0x1fff7a4>
    # count down again (delay impl, note a2 not reloaded)
    400001e0:	167d              addi	a2,a2,-1
    400001e2:	fe7d              bnez	a2,400001e0 <.LBB0_8+0x38>
    # loop back to start
    400001e4:	bfcd              j	400001d6 <.LBB0_8+0x2e>
```

By changing the register spec to `inout`, Rust knows the register is modified and reloads it next time. I added the nomem and nostack options too since the instructions don't touch memory or stack, to match the cortex-m impl. This change fixes codegen for my example:


```
    400001ce:	02faf637          lui	a2,0x2faf
    400001d2:	0816061b          addiw	a2,a2,129
    400001d6:	c10c              sw	a1,0(a0)
    400001d8:	86b2              mv	a3,a2
    400001da:	16fd              addi	a3,a3,-1
    400001dc:	fefd              bnez	a3,400001da <.LBB0_8+0x32>
    400001de:	00052023          sw	zero,0(a0) # 2000000 <.Lline_table_start0+0x1fff779>
    400001e2:	86b2              mv	a3,a2
    400001e4:	16fd              addi	a3,a3,-1
    400001e6:	fefd              bnez	a3,400001e4 <.LBB0_8+0x3c>
    400001e8:	b7fd              j	400001d6 <.LBB0_8+0x2e>

```

Co-authored-by: Adam Greig <adam@adamgreig.com>

103: Fix release year in changelog r=almindor a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

102: Prepare v0.8.0 release r=almindor a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

101: Fix changelog r=dkhayes117 a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

99: Remove uses of unstable features and always use inline assembly r=Disasm a=taiki-e

Currently, the `inline-asm` feature uses unstable features, but by replacing the uses of asm_const with `concat!`+`stringify`, the uses of unstable features can be removed.

https://github.com/rust-embedded/riscv/blob/cd31989ba11d5d64e1addd8aab98bfb00dd927d5/src/lib.rs#L17-L18



Co-authored-by: Taiki Endo <te316e89@gmail.com>

95: Fix copyright year r=dkhayes117 a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

94: csr: inline register reads and type conversations r=dkhayes117 a=luojia65

This pull request adds missing `#[inline]` flags on field read functions and type conversations. Field `#[inline]` marks to enable inline function optimization which speed up the code when used to build kernels and hypervisors.

Please hint me if there are more missing `#[inline]` flags in project `riscv` so I may include them in this fix too.

Off topic: would it be the time to release a 0.7.1 version now? Then we do not need to pin to commit numbers when developing risc-v projects.

r? `@Disasm`

Co-authored-by: luojia65 <me@luojia.cc>

Signed-off-by: luojia65 <me@luojia.cc>

apply clippy suggestions

Signed-off-by: luojia65 <me@luojia.cc>

93: Remove riscv target post fix triple information from asm archive name r=almindor a=MabezDev

For RISCV targets that don't have `unknown-none-elf` in their name. The only bit that matters is the first section anyways.

Co-authored-by: Scott Mabin <scott@mabez.dev>

90: add asm::nop, asm::delay, and delay.rs. r=Disasm a=dkhayes117

update assembly binaries.
update CHANGELOG.md

Co-authored-by: dkhayes117 <dkhayes117@yahoo.com>
Co-authored-by: Daniel Hayes <59458913+dkhayes117@users.noreply.github.com>
Co-authored-by: Vadim Kaushan <admin@disasm.info>

Co-authored-by: Vadim Kaushan <admin@disasm.info>

91: Add inline-asm build to CI, fix build r=dkhayes117 a=Disasm

https://github.com/rust-embedded/riscv/pull/86

 introduced new `asm!` syntax which is enabled with the `inline-asm` feature. However, it doesn't work with current nightly since `asm_const` unstable feature is not enabled. This PR fixes the problem and adds automatic checks to CI.

Co-authored-by: Vadim Kaushan <admin@disasm.info>