`riscv`: support for S-mode

`riscv-rt`: Implement FPU initialization

`riscv-rt`: clean linker script

`riscv-rt`: Rework on exception and interrupt handling

- Replace fmvp.d.x usage with fcvt.d.w as it does not require zfa

riscv-pac crate

This reverts commit 41c50dd4.

`riscv-rt`: remove riscv-target ;`riscv`:update for embedded-hal to 1.0.0-rc.2

embedded-hal 1.0.0-rc.2 introduces backwards incompatible changes.  This change pins the crate to 1.0.0-rc.1.

Add riscv-rt to workspace