Tidy per-ext check-cfg flags

riscv: build: make `cfg` variables more robust

Uses new lint checks for `cfg` variables.

Uses new lint checks for `cfg` variables.

Uses new lint checks for `cfg` variables.

Change which Cargo `CFG` environment variables are used to select the
custom `cfg` variables.

See
https://github.com/rust-embedded/riscv/pull/204#issuecomment-2094089195
for discussion.

`riscv`: register: exports macros for custom CSRs

Exports macros from the `riscv::register::macros` module for external users.

This allows external users to define custom CSR accessor functions.

This is useful for platforms and SoCs with custom CSR registers not
defined in the `riscv` crate.

Resolves: #187

Add Mstatus::from(usize)

Add some utility methods to Mstatus and Mcause

`riscv-rt`: make `abort` weak

This is useful unit tests that want test trap handlers.

Fix mistake in changelog

Fix sip::{set,clear}_ssoft

`riscv-rt`: `_pre_init_trap` and weak symbols

`riscv-rt`: move all the assembly code to `asm.rs`

Cargo metadata for riscv-peripheral

Release new `riscv-peripheral` crate and minor patches

Make fence operations safe

`riscv-rt`: Fix nightly builds

Add `riscv-peripheral` crate

`sfence.vma`, `fence` and `fence.i` just add ordering constraints
load/store operations (between themselves, or other kinds of memory
access). There's no risk of any UB or other unexpected visible changes
in machine state, so we can make these "safe".