43: fix cargo fmt r=Disasm a=almindor

Fixes cargo fmt issues ignoring where needed

Co-authored-by: Ales Katona <ales@katona.me>

40: Document MSRV on README r=Disasm a=eldruin

See: https://github.com/rust-embedded/wg/issues/445



Co-authored-by: Diego Barrios Romero <eldruin@gmail.com>

42: Only checking for necessary extensions when linking r=Disasm a=ilya-epifanov

`M`, `A`, `F` and `D` (as part of `G`) extensions don't matter at all, so generating binaries for them is not necessary, really. Also, if another rust RISC-V target were to come up, this crate would not support it.

In this PR I'm restricting a list of extensions to consider when generating static archives and linking to `I` and `C`.

Co-authored-by: Ilya Epifanov <elijah.epifanov@gmail.com>

41: Fix CI r=almindor a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

38: Release v0.5.6 r=almindor a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

37: Add support for custom vexriscv instructions r=Disasm a=xobs

This adds a new namespace under "registers" to support the custom interrupt controller on vexriscv.

Co-authored-by: Sean Cross <sean@xobs.io>

This script allows Windows users to rebuild the assembly files.

Signed-off-by: Sean Cross <sean@xobs.io>

Signed-off-by: Sean Cross <sean@xobs.io>

VexRiscv contains its own custom registers for external interrupt
mapping.  Add these registers under the `register::vexriscv` namespace,
and prefix the assembly routines with "v-" in order to avoid ambiguity
with e.g. `sip` and `mip` registers.

Signed-off-by: Sean Cross <sean@xobs.io>

36: Release v0.5.5 r=almindor a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

35: Add mideleg register support r=Disasm a=archshift



Co-authored-by: Gui Andrade <gh@archshift.com>

34: mip, satp: Allow writing to these privileged registers r=laanwj a=archshift

Per the RISC-V privileged ISA, these registers should be writable.

Co-authored-by: Gui Andrade <gh@archshift.com>

32: add user trap setup and handling registers r=almindor a=almindor

Adds CSR handlers for user trap setup and handling registers.

Also unifies common shared types.

NOTE: untested, will test on real device ASAP

Co-authored-by: Ales Katona <almindor@gmail.com>

33: Do not use bare-metal v0.2.5 r=almindor a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

30: add riscv32i target r=Disasm a=sbourdeauducq

This adds support for the simplest RISC-V processor possible, which is useful e.g. for experimenting with  FPGA softcore implementations.

Co-authored-by: Sebastien Bourdeauducq <sb@m-labs.hk>