Update assert! logic in mcounteren.rs and scounteren.rs
Fix comment typo on `scounteren`

Add scounteren.rs
Implemented set_hpm and clear_hpm functions
Removed State enum, replaced with bool
Update comments to be more concise

Reformat mod.rs

Update hpm method to use an index from enum

Move mcounteren macros outside of Mcounteren type declaration

update mod.rs

53: Update link (riscv to risc-v) r=Disasm a=aDotInTheVoid



Co-authored-by: Nixon Enraght-Moony <nixon.emoony@gmail.com>

52: Add CSR register `medeleg`; small doc fix r=Disasm a=luojia65

mideleg is at 0x303; medeleg is at 0x302.

Co-authored-by: luojia65 <me@luojia.cc>

51: Fix {S,U}tvec::trap_mode() functions to match Mtvec::trap_mode() r=almindor a=Disasm

See also: https://github.com/rust-embedded/riscv/pull/50#issuecomment-647012575



Co-authored-by: Vadim Kaushan <admin@disasm.info>

50: Update MSRV, release v0.6.0 r=almindor a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

48: Remove vexriscv support. r=Disasm a=khrs



Co-authored-by: Karol Harasim <karol.harasim@gmail.com>

47: Replace asm! with llvm_asm! r=almindor a=Disasm

`asm!` was replaced with a different implementation on nightly, the old one is renamed into `llvm_asm!`

Co-authored-by: Vadim Kaushan <admin@disasm.info>

49: Update dependencies, bump MSRV r=almindor a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

46: Do not panic on unknown trap mode. r=Disasm a=khrs

Some vendors (eg Nuclei) use reserved bits for they own interrupt handling.

Co-authored-by: Karol Harasim <karol.harasim@gmail.com>

Some vendors (eg Nuclei) use reserved bits for they own interrupt handling.

45: Remove #![deny(warnings)] (anti-pattern) r=almindor a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

44: Check code style on CI r=almindor a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

43: fix cargo fmt r=Disasm a=almindor

Fixes cargo fmt issues ignoring where needed

Co-authored-by: Ales Katona <ales@katona.me>

40: Document MSRV on README r=Disasm a=eldruin

See: https://github.com/rust-embedded/wg/issues/445



Co-authored-by: Diego Barrios Romero <eldruin@gmail.com>

42: Only checking for necessary extensions when linking r=Disasm a=ilya-epifanov

`M`, `A`, `F` and `D` (as part of `G`) extensions don't matter at all, so generating binaries for them is not necessary, really. Also, if another rust RISC-V target were to come up, this crate would not support it.

In this PR I'm restricting a list of extensions to consider when generating static archives and linking to `I` and `C`.

Co-authored-by: Ilya Epifanov <elijah.epifanov@gmail.com>

41: Fix CI r=almindor a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>